SAR Logic For Pseudo-Differential Sampling SAR ADC (Using Verilog-HDL)

`timescale        1ns/10ps

module sar_pseudo_differential_switch_v (adc_output,reset, sample_e, sample, dac_input, dac_input_b,state,pd,clk,comp_out);

input         pd;

input        clk;

input        comp_out;

output        [9:0]        adc_output;

output                reset;

output                sample_e;

output                sample;

output        [9:0]        dac_input;

output        [9:0]        dac_input_b;

output                state;

reg        [9:0]        mask;

reg        [9:0]        adc_temp;

reg                reset;

reg                sample_e;

reg                sample;

reg        [9:0]        adc_output;

//        reg        [9:0]        dac_input;

//        reg        [9:0]        dac_input_b;

reg        [2:0]        state;

// state assignment

parameter sPD=0,  sRESET=1, sSAMPLE=2, sCONV1=3, sCONV2=4;

always @(posedge clk) begin

if (pd)

begin        

state <= sPD;

reset <= 0;

sample_e <= 0;

sample <= 0;

mask <= 10'b0000000000;

adc_temp <= 10'b0000000000;

adc_output <= 10'b0000000000;

end

else

case (state)

sPD:         

begin

state <= sRESET;// next clock edge will start

// reseting capacitor array

end

sRESET:        

begin

state <= sSAMPLE;        // next clock edge will trigger

// sample process

reset <= 1;

sample_e <= 0;

sample <= 0;

adc_temp <= 0;

mask <= 10'b0000000000;

end

sSAMPLE:

begin

state <= sCONV1;        // next clock edge will trigger

// MSB conversion

reset <= 0;

sample_e <= 1;

sample <= 1;

#900;

sample_e <= 0;

end

sCONV1:                                        // begin conversion

begin

state <= sCONV2;        // next clock edge will trigger

// MSB-1 conversion

sample_e <= 0;

sample <= 0;

mask <= 10'b1000000000;

end

sCONV2:

begin

if (comp_out) adc_temp <= adc_temp|mask;

mask <= mask>>1;                                                        // sample process

if (mask[0]) begin

state <= sRESET;        // next clock edge will trigger

// reset process

adc_output <= adc_temp;

end

end        

endcase                                 

end // always

assign dac_input = adc_temp | mask;

//assign dac_input_b = ~dac_input & ~pd & state!=sCONV1 & state!=sSAMPLE & state!=sRESET;

assign dac_input_b = ~dac_input & {10{state==sCONV2}} | {10{reset}}  ;

endmodule

Pseudo-differential Sampling SAR ADC

LSB Assigning Cycle DAC (D2A processed) Output Transition

DAC Output Of Unipolar SAR ADC

Note, the last cycle of this successive approximation process will has a step change of FS/2^N (instead of FS/2^(N+1)) or 0

SAR ADC No Output Code Issue

Symptom:

• ADC output code is fixed to 8b'100000; 
• when supply voltage is increased, ADC starts to work properly;
• when clock frequency is lowered, ADC starts to work properly;

Bug:
Driving of ADC clock is weak.
At low voltage, the clock signal at the invertor gates is like a triangle wave, and the tipping point of the invertor is a little higher than half of supply voltage, so clock buffer is not working at all.

When we crank up the supply voltage, the driving capability of driver (is also an invertor) is increased, although the tipping point is also increased with supply voltage, the driver now have enough strength to drive the clock input buffer.

SAR ADC Clock Cycle Allocation

Sample: 1 clock cycle
conversion: Nb clock cycle
(optional) one additional cycle to gate the DAC value as SAR ADC output.

Sampling Frequency Of SAR ADC

Suppose the clock frequency is f_clk, then the sampling frequency of a typical SAR ADC is

or

SAR ADC Timing

After the LSB is set HIGH, SAR ADC will wait one more time slot for the LSB to get settled at the output of comparator.

SAR Logic Verilog-HDL Code

// Created by ihdl
// implemented as a state machine
`timescale 1ns/10ps

module sar_logic(clk,go,valid,result, sample,value,cmp);
input clk; // clock input
input go; // go=1 to perform conversion / like EN signal
output valid; // valid=1 when conversion finished
output [7:0] result; // 8 bit result output
output sample; // to S&H circuit
output [7:0] value; // to DAC
input cmp; // comparitor output
reg [1:0] state; // current state in state machine
reg [7:0] mask; // bit to test in binary search
reg [7:0] result; // hold partially converted result


// state assignment
parameter sWait=0, sSample=1, sConv=2, sDone=3;


// synchronous design
always @(posedge clk) begin
if (!go)
state <= sWait; // stop and reset if go=0
else
case (state) // choose next state in state machine
sWait : // In reality, the sample process starts at this state.
begin
state <= sSample;
result <= 0;
end
sSample :
begin // start new conversion so
state <= sConv; // enter convert state next
mask <= 8'b10000000; // reset mask to MSB only
//result <= 8'b0; // clear result
end
sConv :
begin
// set bit if comparitor indicates input larger than
// value currently under consideration, else leave bit clear
if (cmp) result <= result | mask;


// shift mask to try next bit next time
mask <= mask>>1;

// finished once LSB has been done
if (mask[0]) state <= sDone;
end
sDone : state <= sWait;
endcase
end

assign sample = state==sSample; // drive sample and hold
assign value = result | mask; // (result so far) OR (bit to try)
assign valid = state==sDone; // indicate when finished

endmodule

SAR ADC & Charge Redistribution DAC

There is a extra Vin pin on SAR ADC caps array.