Verilog-HDL power supply

supply0
supply1

AMS Connect Rule File Example

`include "disciplines.vams"
`include "userDisciplines.vams"

`define CONNRULES_18V_FULL_FAST
 `define CONNRULES_18V_FULL
 `define CONNRULES_18V_MID
 `define CONNRULES_18V_BASIC
 `define CONNRULES_FULL_FAST
 `define CONNRULES_FULL
 `define CONNRULES_MID
 `define CONNRULES_BASIC
 `define Vsup  1.8
 `define Vthi  1.2
 `define Vtlo  0.6
 `define Vlow  0
 `define Tr    0.2n
 `define Rlo   200
 `define Rhi   200
 `define Rx    40
 `define Rz    10M
 `define Vdelta      `Vsup/64
 `define Vdelta_tol  `Vdelta/4
 `define Tr_delta    `Tr/20

connectrules ConnRules_1V_full_fast;
  connect L2E_2
      #( .vsup(1), .vlo(0), .tr(0.2n), .tf(0.2n), .rlo(200), .rhi(200), .rx(40), .rz(10M));
  connect E2L_2
      #( .vsup(1), .vthi(0.8), .vtlo(0.2), .tr(0.2n));
  connect Bidir_2
      #( .vsup(1), .vthi(0.8), .vtlo(0.2), .vlo(0), .tr(0.2n), .tf(0.2n), .rlo(200), .rhi(200), .rx(40), .rz(10M));
  connect E2R
      #( .vdelta(`Vsup/64), .vtol(`Vdelta/4), .ttol(`Tr/20));
  connect R2E_2
      #( .vsup(1.8), .vdelta(`Vsup/64), .tr(`Tr/20), .tf(`Tr/20), .rout(200));
  connect ER_bidir
      #( .vdelta(`Vsup/64), .vtol(`Vdelta/4), .ttol(`Tr/20), .tr(`Tr/20), .tf(`Tr/20), .rout(200), .rz(10M));
  connect L2E_2_CPF
      #( .vsup(1.8), .vlo(0), .tr(0.2n), .tf(0.2n), .rlo(200), .rhi(200), .rx(40), .rz(10M));
  connect Bidir_2_CPF
      #( .vsup(1.8), .vthi(1.2), .vtlo(0.6), .tr(0.2n), .tf(0.2n), .rlo(200), .rhi(200), .rx(40), .rz(10M));
endconnectrules

"(* attributes" in Verilog-A

stub

Verilog-A Language Extensions for Compact Modeling

(*  *)

ncelab: *E,CUVDNF (verilog.vams): Could not determine discipline for this expression .

The error goes away by changing all type "voltage" I/Os to type "electrical".

Andrew Buckett suggested to use the resolveto keyword in your connectrules:

connect electrical,voltage resolveto electrical; 

This avoids changing the I/Os and will only impact nodes where you are connecting voltage to electrical disciplines.

Non-Blocking Assignment & Block Assignment

Non-blocking assignments (Q <= A)

• Value to be assigned is computed but saved for later 
• Variable is assigned after all scheduled statements are executed 

A net is not a legal lvalue in this context [9.3.1(IEEE)]

SAR Logic Verilog-HDL Code

// Created by ihdl
// implemented as a state machine
`timescale 1ns/10ps

module sar_logic(clk,go,valid,result, sample,value,cmp);
input clk; // clock input
input go; // go=1 to perform conversion / like EN signal
output valid; // valid=1 when conversion finished
output [7:0] result; // 8 bit result output
output sample; // to S&H circuit
output [7:0] value; // to DAC
input cmp; // comparitor output
reg [1:0] state; // current state in state machine
reg [7:0] mask; // bit to test in binary search
reg [7:0] result; // hold partially converted result


// state assignment
parameter sWait=0, sSample=1, sConv=2, sDone=3;


// synchronous design
always @(posedge clk) begin
if (!go)
state <= sWait; // stop and reset if go=0
else
case (state) // choose next state in state machine
sWait : // In reality, the sample process starts at this state.
begin
state <= sSample;
result <= 0;
end
sSample :
begin // start new conversion so
state <= sConv; // enter convert state next
mask <= 8'b10000000; // reset mask to MSB only
//result <= 8'b0; // clear result
end
sConv :
begin
// set bit if comparitor indicates input larger than
// value currently under consideration, else leave bit clear
if (cmp) result <= result | mask;


// shift mask to try next bit next time
mask <= mask>>1;

// finished once LSB has been done
if (mask[0]) state <= sDone;
end
sDone : state <= sWait;
endcase
end

assign sample = state==sSample; // drive sample and hold
assign value = result | mask; // (result so far) OR (bit to try)
assign valid = state==sDone; // indicate when finished

endmodule