SAR Logic For Pseudo-Differential Sampling SAR ADC (Using Verilog-HDL)

`timescale        1ns/10ps

module sar_pseudo_differential_switch_v (adc_output,reset, sample_e, sample, dac_input, dac_input_b,state,pd,clk,comp_out);

input         pd;

input        clk;

input        comp_out;

output        [9:0]        adc_output;

output                reset;

output                sample_e;

output                sample;

output        [9:0]        dac_input;

output        [9:0]        dac_input_b;

output                state;

reg        [9:0]        mask;

reg        [9:0]        adc_temp;

reg                reset;

reg                sample_e;

reg                sample;

reg        [9:0]        adc_output;

//        reg        [9:0]        dac_input;

//        reg        [9:0]        dac_input_b;

reg        [2:0]        state;

// state assignment

parameter sPD=0,  sRESET=1, sSAMPLE=2, sCONV1=3, sCONV2=4;

always @(posedge clk) begin

if (pd)

begin        

state <= sPD;

reset <= 0;

sample_e <= 0;

sample <= 0;

mask <= 10'b0000000000;

adc_temp <= 10'b0000000000;

adc_output <= 10'b0000000000;

end

else

case (state)

sPD:         

begin

state <= sRESET;// next clock edge will start

// reseting capacitor array

end

sRESET:        

begin

state <= sSAMPLE;        // next clock edge will trigger

// sample process

reset <= 1;

sample_e <= 0;

sample <= 0;

adc_temp <= 0;

mask <= 10'b0000000000;

end

sSAMPLE:

begin

state <= sCONV1;        // next clock edge will trigger

// MSB conversion

reset <= 0;

sample_e <= 1;

sample <= 1;

#900;

sample_e <= 0;

end

sCONV1:                                        // begin conversion

begin

state <= sCONV2;        // next clock edge will trigger

// MSB-1 conversion

sample_e <= 0;

sample <= 0;

mask <= 10'b1000000000;

end

sCONV2:

begin

if (comp_out) adc_temp <= adc_temp|mask;

mask <= mask>>1;                                                        // sample process

if (mask[0]) begin

state <= sRESET;        // next clock edge will trigger

// reset process

adc_output <= adc_temp;

end

end        

endcase                                 

end // always

assign dac_input = adc_temp | mask;

//assign dac_input_b = ~dac_input & ~pd & state!=sCONV1 & state!=sSAMPLE & state!=sRESET;

assign dac_input_b = ~dac_input & {10{state==sCONV2}} | {10{reset}}  ;

endmodule